Vaire moves to its second reversible chip
With net energy recovery already on silicon, the reversible-computing startup turns from proving the principle to making it competitive — a second chip built around logic, not just a resonator.
From principle to product
In 2025 Vaire Computing's first test chip, codenamed Ice River, did something no commercial part had done before: it ran an adiabatic circuit that recovered more energy than it spent driving it. Built in ordinary 22 nm CMOS, the chip's resonator returned charge to the supply instead of dumping it as heat, posting energy-recovery ratios of about 1.77 for a capacitor bank and 1.41 for an adder — both comfortably above the break-even line of 1.0.
Demonstrating recovery is one thing; building a useful processor out of it is another. Vaire's second tapeout shifts the emphasis from the power clock to the logic itself, chasing not only energy recovery but competitive power, performance and area — the metrics any chip is judged by.
The roadmap into 2026
The company's public roadmap points to a more advanced prototype during 2026 and market-ready reversible chips around 2028, aimed first at the workloads where energy is the binding constraint — large, parallel AI inference in power-limited data centres. The long-horizon target it talks about is dramatic: efficiency gains of up to several thousand times for suitable workloads, as conventional scaling runs out of room.
Those are long bets, and reversible logic still has to clear real engineering hurdles around clocking, density and tooling. But the direction of travel is clear: energy-recovery computing has left the whiteboard and is now an engineering problem, not a physics question.
Source
Reported by EE Times and analysed by Data Center Dynamics; background at Interesting Engineering and Vaire Computing.